IEEE 802.3-2008 compliant XGMII interface (Clause46) to talk to an external PHY.Independent 64-bit or 128-bit scatter-gather DMA for Transmit and Receive operations.Direct Connection to either 64-bit or 128-bit AHB or AXI Interface Master Interface and 32-bit AHB or AXI Target Interface.Option to operate at Independent Transmit and Receive 161.13 MHz Clock when interfacing with the XG-64B66B PCS Module.Operates at Independent Transmit and Receive 156.25 MHz Clocks as defined in the Clause 46 of the IEEE 802.3-2008 Specification.See the Feature tab below for a full list of features. Other features of the XGMAC IP include generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection. It also includes dynamic generation, checking, and stripping of FCS field, and automatic pad field insertion. The XGMAC IP supports MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. The 10 Gigabit Ethernet XGMAC IP also provides enhanced programmable features for minimizing applications complexity and pre/post message processing. The XGMAC core supports the XGMII interface and a MDIO/MDC (Management Data Input/ Output and Management Data Clock) management interface provides control and management functions to external PHY devices. An AHB/AXI master and a 64-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance. The XGMAC IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. The 10 Gigabit Ethernet XGMAC also supports flow control operation by supporting generation and decoding of PAUSE control frames and supports generation of Management frames on MDC/MDIO signals to communicate with an external PHY device. The XGMAC provides features that include transmit and receive message data encapsulation, framing, error code detection, dynamic FCS generation and calculation on frame by frame basis, automatic pad insertion and deletion to enforce minimum frame size requirements. The XGMAC operates at a speed of 10 Gbps in full duplex mode only. The 10 Gigabit Ethernet IP core is designed for applications such as integrated networking devices, host bus adapters, PCI-Express Ethernet controllers, and Ethernet adapter cards. Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA.
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